Regviz

Espressif Systems /ESP32-P4 /LP_ADC /READER2_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as READER2_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-P4/LP_ADC/READER2_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SAR2_CLK_DIV0SAR2_WAIT_ARB_CYCLE 0 (SAR2_CLK_GATED)SAR2_CLK_GATED 0SAR2_SAMPLE_NUM0SAR2_EN_PAD_FORCE_ENABLE 0 (SAR2_DATA_INV)SAR2_DATA_INV 0 (SAR2_INT_EN)SAR2_INT_EN

Description

Control the read operation of ADC2.

Fields

SAR2_CLK_DIV

Clock divider.
SAR2_WAIT_ARB_CYCLE

Wait arbit stable after sar_done.
SAR2_CLK_GATED

N/A
SAR2_SAMPLE_NUM

N/A
SAR2_EN_PAD_FORCE_ENABLE

Force enable adc en_pad to analog circuit 2’b11: force enable .
SAR2_DATA_INV

Invert SAR ADC2 data.
SAR2_INT_EN

Enable saradc2 to send out interrupt.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data